VCS模擬指南

admin @ 2014-03-26 , reply:0

     VCS-verilog compiled simulator是synopsys公司的產品.其模擬速度相當快,而且支持多種調用方式;使用的步驟和modelsim類似,都要先做編譯,再調用模擬.
     Vcs包括兩種調試界面:Text-based:Command Line Interface(CLI) 和 GUI-based(VirSim);模擬主要的兩個步驟是編譯,運行:
>vcs design.v
//編譯verilog的源文件並且生成一個可執行文件simv
>simv
//運行simv
一般情況下都存在vcs 做編譯的時候的compile_time_options和運行時候的run_time_options,這些我們在下面再具體介紹.

一.VCS的三種調試模式
使用vcs存在三種調試模式:CLI調試模式,VirSim交互調試模式和VirSim后處理調試模式.下面舉例說明:
1. CLI調試模式
CLI調試模式存在兩種調用方法,一種是編譯后馬上執行,一種是把編譯執行分開處理
>vcs source.v +cli+3 –R –s
或者
>vcs source.v +cli+3
>simv source.v –s
其中 +cli+[1 2 3 4]是指調試時候交互調試的能力.
+cli+[<module_name>=]1|2|3|4
Enable CLI debugging.
1 enables you to see the values of nets and registers and deposit values to registers.
2 also enables breakpoints on value changes of nets and registers.
3 also enables you to force a value on nets.
4 also enables you to force a value on a register.
You can specify a module to enable CLI debugging only for instances of the module.
-line 能夠支持單步調試 但是這些都是會增加運行時間的.
這裡不詳細介紹CLI 命令具體可以參考usrerguide.注意我們也可以把CLI的命令寫成一個script的文件在vcs編譯時調用.
>vcs source.v –R –s –include script_file
或者在cli下調用cli>source script_file

2. VirSim交互調試模式
啟動VirSim交互調試模式和調用CLI一樣也是有兩中方法.
>vcs source.v –RI –line +vcsd +cfgfile+filename
或者
>vcs source.v –I –line +vcsd
>vcs source.v -RIG +cfgfile+filename
其中-RI 作用有兩個:編譯生成可以在VirSim中可執行的文件並且編譯后馬上啟動Virsim;
要編譯成可以在VirSim中可執行的文件必須在編譯階段加-I,在要生成vcd或vpd時這個參數一定要添加;-RIG通過一個已編譯完成的默認的simv文件啟動Virsim,在啟動之前一定要通過vcs –RI或者-I對源文件做過編譯.
使用vcs編譯源文件之後會發現目錄下多了simv和/csrc等文件,其中simv是默認的可執行文件,可以在vcs做編譯的時候 –o filename改變輸出的名字,/csrc是存的增量編譯的結果,/simv.daidir如果設置中使用到了PLI就會創建.
具體如何使用VirSim做交互調試這裡也不具體介紹,可以參考VirSim的userguide和vcs安裝下面的doc的tutorial.

3. VirSim的后處理調試模式
注意什麼時候用后處理調試模式,什麼時候使用交換模式那?在初步模擬的過程使用交
互模式,若是調試一個成熟的設計或者很多人一起做調試這樣子可以使用post-processing mode.其主要的方法是通過模擬運行dump數據在vcd或者vpd文件中,運行結束后通過vcd或者vpd觀察運行過程的情況,交互調試能力相對較差,但是通過記錄的數據可以觀察出其中異常的地方;也就是包括兩個步驟Write VCD+ file,View result.
>vcs source.v –line –R -PP +vcsd
其中-R自動運行並且生成vcd+文件
-PP編譯的時候是faster VirSim post_processing
>vcs –RPP source.v +vpdfile+vcdplus.vpd
注意:VirSim只能處理VCD+ file.VCD文件可以被轉換成VCD+格式的文件.
VCD+和VCD有什麼不一樣那?更快,更小.
VCD+系統任務可以在testbench中使用也可以在模擬的時候添加.(注意使用到這些系統函數時,在vcs編譯的時候一定要添加-I或者-RI.)
$vcdpluson(level_number,module_instance,….|net_or reg,….)
level_numbers
指定記錄的層次
0- 記錄整個指定module_instance的所有信號
1- 記錄指定module_instance頂層信號
n- 記錄從頂層開始到下面的n層例化模塊的信號
module_instance 指定例化名
net_ or reg 指定特定的wire或者reg作為記錄的對象,默認是所有信號.
$vcdplusoff(module_instance,….|net_ or reg,…)
其他系統函數可以參見VCS quick reference.

二. 其他情況
注意區別的兩個方面:
1. –R –I 不同於-RI
-R –I是編譯成VirSim的可執行文件而且馬上運行模擬, -RI是編譯成VirSim的可執行文件並且調用VirSim.
2. –R –PP 不同於-RPP
-R –PP是編譯成VirSim的可執行文件並且在運行的時候加快輸出VCD+文件
-RPP是在存在VCD+的條件下調用VirSim進行post processing的調試.
門級模擬需要反標SDF文件,可以在testbench中添加$sdf_annotate系統函數.並且在編譯的時候注意要使用standcell的模擬庫.

Compile-Time Options
********************
-f <filename>
Specifies a file that contains a list of pathnames to source files
and compile-time options.
-F <filename>
Same as the -f option but allows you to specify a path to the file
and the source files listed in the file do not have to be absolute
pathnames.
-h
Displays a succinct description of the most commonly used compile-time
and runtime options.
-l <filename>
(lower case L) Specifies a log file where VCS records compilation
messages and runtime messages if you include the -R, -RI, or
-RIG options.
-line
Enables stepping through the code and source line breakpoints in VirSim.
-M
Enables incremental compilation, but do not overwrite the makefile.
-Mupdate
Enable incremental compilation and overwrite the make file.
-notice
Enables verbose diagnostic messages.
-o <name>
Specifies the name of the executable file that is the product of
compilation. The default name is simv (simv.exe on Windows).
-ova_cov
Enables functional coverage.
-P <pli.tab>
Specifies a PLI table file.
-R
Run the executable file immediately after VCS links together the
executable file. You can add any runtime option to the vcs command
line.
-s
Stop simulation just as it begins. Use this option with the -R and
+cli options.
-timescale=<time_unit>/<time_precision>
If only some source files contain the `timescale compiler directive
and the ones that don't appear first on the vcs command line, use
this option to specify the time scale for these source files.
-V
Enables the verbose mode.
-v <filename>
Specifies a Verilog library file to search for module definitions.
-vera
Specifies the standard VERA PLI table file and object library.
-y <directory_pathname>
Specifies a Verilog library directory to search for module
definitions.
+2state
Enables 2 state simulation.
+cli+[<module_name>=]1|2|3|4
Enable CLI debugging.
1 enables you to see the values of nets and registers and deposit
values to registers.
2 also enables breakpoints on value changes of nets and registers.
3 also enables you to force a value on nets.
4 also enables you to force a value on a register.
You can specify a module to enable CLI debugging only for instances
of the module.
+define+<macro_name>=<value>
Defines a text macro. Test for this definition in your Verilog
source code using the `ifdef compiler directive.
+incdir+<directory>
Specifies the directories that contain the files you specified with
the `include compiler directive. You can specify more that one
directory, separating each path name with the + character.
+libext+<extension>
Specifies that VCS only search the source files in a Verilog library
directory with the specified extension. You can specify more than one
extension, separating each extension with the + character.
For example, +libext++.v specifies searches library files with no
extension and library files with the .v extension.
Enter this option when you enter the -y option.
+maxdelays
Use maximum value when min:typ:max values are encountered in delay
specifications SDF files.
+mindelays
Use minimum value when min:typ:max values are encountered in delay
specifications and SDF files.
+notimingcheck
Suppresses timing checks in specify blocks.
+plusarg_ignore
Also enter this option in the file that you specify with the -f option
so that VCS does not pass to the simv executable or to VirSim the
options that follow in the file. Use this option with the
+plusarg_save option to specify that other options should
not be passed.
+race
Specifies that VCS generate a report, during simulation, of all the
race conditions in the design and write this report in the race.out
file.
+race=all
Analyzes the source code during compilation to look for coding
styles that cause race conditions.
+rad or +rad+2
Performs aggressive optimizations on your design.
+rad+1 or +radlite or +radlight
Performs less aggressive optimizations on your design.
+v2k
Enables the use of new Verilog constricts in the 1364-2001 standard.

Runtime Options
***************
-i <filename>
Specifies a file containing CLI commands that VCS executes when
simulation starts.
-l <filename>
Specifies writing all messages from simulation to the specified
file as well as displaying these messages in the standard output.
This option begins with the letter "l" (lowercase "L") for log file.
-ova_cov
Enables functional coverage reporting.
-s
Stops simulation just as it beings, and enters interactive mode.
Use with the +cli+<number> option.
-V
Verbose mode. Print VCS version and extended summary information.
Prints VCS compile and run-time version numbers, and copyright
information, at start of simulation.
-vcd <filename>
Sets the output VCD file name to the specified file.
The default filename is verilog.dump.
A $dumpfile system task in the Verilog source code will override
this option.
+maxdelays
Species using the compiled SDF file for maximum delays generated
by the +allmtm compile-time option.
Also specifies using maximum delays for SWIFT VMC or SmartModels
or Synopsys hardware models if you also enter the
+override_model_delays runtime option.
+mindelays
Specifies using the compiled SDF file for minimum delays generated
by the +allmtm compile-time option.
Also specifies using minimum delays for SWIFT VMC or SmartModels
or Synopsys hardware models if you also enter the
+override_model_delays runtime option.
+notimingcheck
Suppress timing checks.
+override_model_delays
Enables you to use the +mindelays, +typdelays, or +maxdelays runtime
options to specify timing for SWIFT SmartModels or Synopsys hardware
models.
+sdfverbose
Enables the display of more than ten warning and ten error messages
about SDF back annotation.
+vcs+dumpoff+<t>+<ht>
Turn off value change dumping ($dumpvars system task) at time <t>.
<ht> is the high 32 bits of a time value greater than 32 bits.
+vcs+dumpon+<t>+<ht>
Suppress $dumpvars system task until time <t>.
<ht> is the high 32 bits of a time value greater than 32 bits.
+vcs+dumpvarsoff
Suppress $dumpvars system tasks.
+vcs+finish+<t>+<ht>
Finish simulation at time <t>.
<ht> is the high 32 bits of a time value greater than 32 bits.

Options for Using VirSim Interactively or in Post-Processing
************************************************************
+cfgfile+<filename>
Specifies using a configuration file that you recorded in a
previous session with VirSim.
+vslogfile[+<filename>]
Enables logging of VirSim commands in a VirSim log file. If you do not
specify a filename, the log is automatically saved to the working
directory as VirSim.log.
Options For Using VirSim
************************
the following are options for using VirSim. You enter them on the
vcs command line and also specify the source files.
Options for Using VirSim interactively with VCS
+++++++++++++++++++++++++++++++++++++++++++++++
-RI
Run Interactive. Starts VirSim immediately after compilation.
-RIG
Run Interactive Debug. Start VirSim using an existing executable
file (such as the simv or simv.exe file). VCS does no compilation.
+sim+<simv_name>
Use with the -RIG option. You need this option to specify the name
of the simv executable file that isn't named simv but has a different
name that you specified with the -o compile-time option.
+vslogfilesim[+<filename>]
Enables the logging of VCS communication messages in the VirSim log
file. If you use both +vslogfile and +vslogfilesim, VirSim commands
and VCS messages are saved to the same file.
If you do not specify a filename, the log is automatically saved
to the working directory as VirSim.log.
+vpdfile+<filename>
At runtime, defines an alternative name of the VCD+ file that VCS
writes instead of the default name vcdplus.vpd.

Options for Using VirSim in Post-Processing
+++++++++++++++++++++++++++++++++++++++++++
-RPP
Run Post-Processing mode. Starts VirSim for post-processing a VCD+
file.
+vcdfile+<filename>
Specifies the VCD file you want to use for post-processing.
+vpdfile+<filename>[+start+<start_time>+end+<end_time>]
In post-processing, specifies the VCD+ file you wish to view in
VirSim. The optional +start+<start_time> and +end+<end_time>
arguments specify you only want VirSim to display the results
from between these simulation times.

Options for Specifying How VCS Writes the VCD+ File
+++++++++++++++++++++++++++++++++++++++++++++++++++
-PP
Enables system tasks and options for VCD+ files and optimizations
for faster post-processing.
-I
Enables system tasks and options for VCD+ files.
+vpdbufsize+<MB>
VCS uses an internal buffer to store value changes before it writes
them to the VCD+ file on disk. VCS makes this buffer size either 5
MB or large enough to record 15 value changes for all nets and
registers in your design, which ever is larger.
You can use this option to override the buffer size that VCS
calculates for the buffer size. You specify a buffer size in
megabytes.
+vpddrivers
Tells VCS to record the values of all the drivers of all the nets.
+vpdfilesize+<MB>
Specifies the maximum size of the VCD+ file. When VCS reaches this
limit, VCS overwrites the oldest simulation history data in the file
with the newest.
+vpdignore
Tells VCS to ignore $vcdplus system tasks so VCS does not write a
VCD+ file.
+vpdports
Tells VCS to record, in the VCD+ file, the port direction of signals
that are ports.
+vpdnocompress
Disables the automatic compressing of the data in VCD+ files.
+vpdupdate
If VCS is writing a VCD+ file during simulation, this option enables
you to have VCS halt writing to the VCD+ file while the simulation
is running and so that you can view the recorded results in VirSim.
This option enables you to use the update feature in VirSim.
+vpdnostrengths
Disables recording strength information in the VCD+ file.

Options For CAlling The vcd2vpd and vpd2vcd Utilities
*****************************************************
-vcd2vpd <vcd_filename> <vcdplus_filename>
Tells VCS to find and run the vcd2vpd utility that converts a VCD
file to a VCD+ file. VCS inputs to the utility the specified VCD
file and the utility outputs the specified VCD+ file.
-vpd2vcd <vcdplus_filename> <vcd_filename>
Tells VCS to find and run the vpd2vcd utility that converts a VCD+
file to a VCD file. VCS inputs to the utility the specified VCD+
file and the utility outputs the specified VCD file.
The Virsim debugger and the vpd2vcd and vcd2vpd translator utilities
are best invoked via the vcs command line.

Summary of vcs options for the $vcdpluson tasks:
------------------------------------------------
-I enable interactive/postprocessing debugging capabilities
-PP enable optimizer postprocessing capabilities for vcd+
+vcsd enable the VCS DKI (Direct Kernel Interface); +vpdports,
+vpddrivers, output and interactive
simulation currently are not available in +vcsd mode.

Summary of vcs options for the Virsim GUI:
------------------------------------------
-RI after compilation, run simulation under Virsim (implies -I)
-RIG run simulation under Virsim without compiling (executable has to exist)
-RPP run Virsim in postprocessing mode (requires file created by $vcdpluson)

Additional Virsim Verilog and $vcdpluson flags:
-----------------------------------------------
VirSim 4.3.R11 Virtual Simulator Environment
Copyright (C) 1993-2003 by Synopsys, Inc.
Licensed Software. All Rights Reserved.
Usage: vcs [-RI|-RIG|-RPP] [[+vpdfile+<vpdname>]...] [[+vcdfile+<vcdname>]...] [[+cfgfile+<cfgname>]...]
[sim-opts] [vpd-opts-to-pli] [other-opts] files
+vpdfile+<vpdname> Multiple VPD files can be opened using several
+vpdfile+ commands
+vcdfile+<vcdname> Multiple VCD files can be opened using several
+vcdfile+ commands
+cfgfile+<cfgname> Multiple (incremental) configuration files can be loaded
sim-opts:
+sim+<simulator-path> Sets simulator path name
+simtype+<simulator> Sets simulator type exactly as listed in Simulator
Invocation Dialog
+simargs+<parameters> Sets additional simulator arguments. Double quotes
around multiple arguments.
+simargs+"+vpdfile+<vpdname>" Sets name of VPD file to be created by VCD+ PLI
vpd-opts-to-pli: Options for VCD+ generation by an interactive
simulation run started by virsim
+vpdports Stores port type information for hierarchy
+vpddrivers Stores data for changes on drivers of resolved nets
+vpdbufsize+<#MB> Changes the default size of the internal VCD+ buffer
+vpdfilesize+<#MB> Sets file size when storing data in wraparound mode
+vpdupdate Enables VPD file locking
+vpdignore Tells simulator to ignore all calls to generate VPD
+vslogfile Enables message logging. Does not log simulation communication messages
+vslogfile+<filename> Enables message logging. Logs messages in filename
+vslogfilesim Enables logging of simulation communication messages
other-opts: Sets regular options to compile verilog code
+v2k Enables supported verilog 2000 additions
files: Verilog source code file(s) list

Summary of vcd2vpd options:
---------------------------
Usage: vcs -vcd2vpd <options> <evcd_options> <vcd_file> <vpd_file>
<options>
-b# Buffer size in KB used to store Value Change Data before
writing it to disk.
-f# Maximum output file size in KB. Wrap around occurs if
the specified file size is reached.
-h Translate hierarchy information only.
-m Give tranlsation metrics during translation.
-q Suppress printing of copyright and other informational messages.
+deltacycle Add delta cycle information to each signal value change.
+glitchon Add glitch event detection data.
+nocompress Turn data compression off.
+nocurrentvalue Do not include object's current value at the beginning of each VCB.
<evcd_options>
+dut+<dut_prefix> Modifies the string identifier for the Device-Under-Test
half of the split signal. Default is "DUT".
+tf+<tf_prefix> Modifies the string identifier for the Test-Fixture
half of the split signal. Default is "TF".
+indexlast Appends the bit index of a vector bit as the last
element of the name.

Summary of vpd2vcd options:
---------------------------
Usage: vcs -vpd2vcd <vpd_file> [<vcd_file>]
Summary of vpd2vcd command line options
-h Translate hierarchy information only.
-q Suppress printing of copyright and other informational messages.
-s Allow sign extension for vectors. Reduces size of <vcd_file>.
-x Expand vector variables to full length when displaying
$dumpoff value blocks.
+zerodelayglitchfilter Zero delay glitch filtering for multiple value changes within
the same time unit.
+morevhdl Translates the vhdl types that are not directly mappable to
verilog types in addition to the ones that are mappable.
+start+<value> Translate value changes starting after start time <value>
+end+<value> Translate value changes ending before end time <value>
(Note) If both start and end values are input, value changes
occuring between start and end time are translated.




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