testbench書寫過程

admin @ 2014-03-26 , reply:0

各種文件的說明

  • Netlist Files:HDL code??合成後?出的.v?n,或是?比?路跑HSPICE的.sp?n
  • Stimulus Files:HDL??的testbench.v??value change dump?成.vcd,.vcd再??VTRAN?成vector file (.vec)
                            .vec 是???用?眇j?netlist?input pattern用的
  • Configuration File:用?碓O定??模?M?r,要?X取哪些?的哪些?息(如??夯螂?流),以?Υ嬖?out?.log
                                 (如果是用GUI介面,可以不需要????n案)
  • Technology file:NanoSim uses a tech. file in place of MOS models during simulation
  • .out File  :?絛心?M後的?出?n案,供turboWave直接?取以?示????流波形
  • .fsdb File:?絛心?M後的?出?n案,供turboWave直接?取以?示????流波形
  • .log File  :模?M?果的?出,?面有耗?情?r的report

由於NanoSim是Transistor-level simulator,要?絛?anoSim有?追N方式

  • 提供?比?路的spice netlist (.sp or .spi)?MOS spice module (含????囟紉?格) -- ?比模?M
  • 提供?滴渾?路的gate-level netlist (.v),cell-base spice simulation module (not cell-base Verilog simulation module)?MOS spice module (含????囟紉?格) -- ?滴荒?M
  • 提供?比?路的spice netlist (.sp or .spi)??滴渾?路的gate-level netlist (.v),以VCS搭配NanoSim做?比??滴壞幕旌夏?M

書寫testbench之前要了解測試單元的設計規範,要很清楚規範並且要有測試文檔(test bench 的結構和測試情況)
以一個四位計數器為例,計數器程序如下:
//-----------------------------------------------------
// Design Name : counter
// File Name   : counter.v
// Function    : 4 bit up counter
// Coder       : Deepak
//-----------------------------------------------------
module counter (clk, reset, enable, count);
input clk, reset, enable;
output [3:0] count;
reg [3:0] count;
always @ (posedge clk)
if (reset == 1'b1) begin
  count <= 0;
end else if ( enable == 1'b1) begin
  count <= count + 1;
end

endmodule 
test plan 如下:本test bench是自動檢測測試,我們的 test bench 測試環境如下圖所示: 
 
待測試的設計(DUT)是 test bench中的一部分, 其中 test bench 有 clock generator, reset generator, enable logic generator, and compare logic, which basically calculate the expected count value of counter and compare the output of counter with calculated value.
測試的情況(根據設計說明確定,應盡量使測試完全):

  •  Reset Test : We can start with reset de-asserted, followed by asserting reset for few clock ticks and deasserting the reset, See if counter sets its output to zero.
  •  Enable Test: Assert/deassert enable after reset is applied.
  •  Random Assert/deassert of enable and reset.

Test bench設計過程
1. 通式,test bench也是一個模塊,其中包括module名,一般是測試設計名加_tb;進行待測設計的例化;對初始埠的初始化;時鐘的設計;測試結果的輸出。具體如下:

  1 module counter_tb;
  2   reg clk, reset, enable;
  3   wire [3:0] count;
  4    
  5   counter U0 (
  6   .clk    (clk),
  7   .reset  (reset),
  8   .enable (enable),
  9   .count  (count)
 10   );
 11    
 12   initial begin
 13     clk = 0;
 14     reset = 0;
 15     enable = 0;
 16   end
 17    
 18   always 
 19     #5 clk = !clk;
 20    
 21   initial  begin
 22     $dumpfile ("counter.vcd");
 23     $dumpvars;
 24   end
 25    
 26   initial  begin
 27     $display(" time, clk, reset, enable, count");
 28     $monitor("%d, %b, %b, %b, %d",$time, clk,reset,enable,count);
 29   end
 30    
 31   initial
 32   #100 $finish;
 33    
 34   //Rest of testbench code after this line
 35    
 36 endmodule

時鐘設計的方法:
系統函數的說明:
$dumpfile is used for specifying the file that simulator will use to store the waveform, that can be used later to view using waveform viewer.
$dumpvars basically instructs the Verilog compiler to start dumping all the signals to "counter.vcd".
$display is used for printing text or variables to stdout (screen), is for inserting tab. Syntax is same as printf.
$monitor keeps track of changes to the variables that are in the list (clk, reset, enable, count). When ever anyone of them changes, it prints their value, in the respective radix specified.
$finish is used for terminating simulation after #100 time units (note, all the initial, always blocks start execution at time 0)

2. 加rest邏輯
假如rest是非同步的(activate reset anytime during simulation)利用'events'實現,events can be triggered, and also monitored to see, if a event has occurred.
  1 event reset_trigger;
  2   event  reset_done_trigger;
  3    
  4   initial begin
  5     forever begin
  6       @ (reset_trigger);
  7       @ (negedge clk);
  8       reset = 1;
  9       @ (negedge clk);
 10       reset = 0;
 11       -> reset_done_trigger;
 12     end
 13   end
code our reset logic in such a way that it waits for the trigger event "reset_trigger" to happen, when this event happens, reset logic asserts reset at negative edge of clock and de-asserts on next negative edge as shown in code below. Also after de-asserting the reset, reset logic triggers another event called "reset_done_trigger". This trigger event can then be used at some where else in test bench to sync up.

3. test case:每一個test case 在一個initial模塊里,在一個測試中有多個test
case,可以利用 a event like "terminate_sim" and execute $finish only when this event is triggered. We can trigger this event at the end of test case execution. The code for $finish now could look as below.
例如 在加之前是這樣的

  1  initial 
  2   begin: TEST_CASE
  3     #10 -> reset_trigger;
  4     @ (reset_done_trigger);
  5     @ (negedge clk);
  6     enable = 1;
  7     repeat (10) begin
  8       @ (negedge clk);
  9     end
 10     enable = 0;
 11   end 
加上之後
  1 initial 
  2   begin: TEST_CASE
  3     #10 -> reset_trigger;
  4     @ (reset_done_trigger);
  5     @ (negedge clk);
  6     enable = 1;
  7     repeat (10) begin
  8       @ (negedge clk);
  9     end
 10     enable = 0;
 11     #5 -> terminate_sim;
 12   end

4. 實現自動檢驗測試結果
首先功能上模擬待檢測的設計。
然後加上檢驗邏輯,當檢驗邏輯結果和待檢測設計結果不同時輸出錯誤,並且停止模擬。

 1 always @ (posedge clk)
 2   if (count_compare != count) begin
 3     $display ("DUT Error at time %d", $time);
 4     $display (" Expected value %d, Got Value %d", count_compare, count);
 5     #5 -> terminate_sim;
 6   end
最後在所有上面的都書寫完畢后將程序中的display, monitor去掉,就得到最終的test bench。
最終結果如下:
///////////////////////////////////////////////////////////////////////////
// MODULE               : counter_tb                                     //
// TOP MODULE           : --                                             //
//                                                                       //
// PURPOSE              : 4-bit up counter test bench                    //
//                                                                       //
// DESIGNER             : Deepak Kumar Tala                              //
//                                                                       //
// Revision History                                                      //
//                                                                       //
// DEVELOPMENT HISTORY  :                                                //
//               Rev0.0 : Jan 03, 2003                                   //
//                        Initial Revision                               //
//                                                                       //
///////////////////////////////////////////////////////////////////////////
module counter_tb;

reg clk, reset, enable;
wire [3:0] count;
reg dut_error;

counter U0 (
.clk    (clk),
.reset  (reset),
.enable (enable),
.count  (count)
);

event reset_enable;
event terminate_sim;

initial
begin
 $display ("###################################################");
 clk = 0;
 reset = 0;
 enable = 0;
 dut_error = 0;
end

always
  #5 clk = !clk;

initial?
begin
  $dumpfile ("counter.vcd");
  $dumpvars;
end

initial
@ (terminate_sim)  begin
 $display ("Terminating simulation");
 if (dut_error == 0) begin
   $display ("Simulation Result : PASSED");
 end
 else begin
   $display ("Simulation Result : FAILED");
 end
 $display ("###################################################");
 #1 $finish;
end

event reset_done;

initial
forever begin
 @ (reset_enable);
 @ (negedge clk)
 $display ("Applying reset");
   reset = 1;
 @ (negedge clk)
   reset = 0;
 $display ("Came out of Reset");
 -> reset_done;
end

initial begin
  #10 -> reset_enable;
  @ (reset_done);
  @ (negedge clk);
  enable = 1;
  repeat (5)
  begin
   @ (negedge clk);
  end
  enable = 0;
  #5 -> terminate_sim;
end

reg [3:0] count_compare;

always @ (posedge clk)
if (reset == 1'b1)
 count_compare <= 0;
else if ( enable == 1'b1)
 count_compare <= count_compare + 1;

always @ (negedge clk)
if (count_compare != count) begin
  $display ("DUT ERROR AT TIME%d",$time);
  $display ("Expected value %d, Got Value %d", count_compare, count);
  dut_error = 1;
  #5 -> terminate_sim;
end
endmodule




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